1. Field of the Invention
The present invention relates to a gate circuit having a complementary transistor structure comprising transistors of different conductivity types connected in series respectively between two power source terminals and an output terminal, sharing a gate connected to an input terminal, the transistors of different conductivity types each comprising plural transistors, and the plural transistors being connected in series between each of the two power source terminal and the output terminal, and also relates to a delay circuit using the gate circuit.
2. Description of the Related Art
A known conventional delay circuit uses a gate circuit (inverter) based on a complementary transistor structure. FIG. 4 shows a first example of a gate circuit used in such a conventional delay circuit. FIG. 5 shows a mount (layout) structure of the same circuit. Further, the conventional delay circuit is constructed by connecting serially a plurality of gate circuits each shown in FIG. 4 (for example, see Patent Literature 1).
The layout shown in FIG. 5 is constructed including, for example: a P-type diffusion layer 3 provided in an N-well region 2 formed at a part of a P-type silicon substrate 1; an N-type diffusion layer 4 provided apart from the P-type diffusion layer 3, outside the N-well region; a gate 7 provided bridging the two diffusion layers 3 and 4 and having a connection via 6 formed in the center portion and connected to an input terminal (metal wire layer) 5; power source terminals (power source wire layer) 10 and 11 provided near the two ends of the gate 7 and connected to the diffusion layers 3 and 4 through connection vias 8 and 9; and an output terminal 14 as a metal wire layer which connects the two diffusion layers 3 and 4 to each other though connection vias 12 and 13.
Another (second) known example of the conventional delay circuit also uses a gate circuit (inverter) based on a complementary transistor structure. Each of transistors having different conductivity types and forming the complementary transistor structure is further constructed by plural transistors. These plural transistors are connected in series between a power source terminal and an output terminal. FIG. 6 shows a gate circuit used in such a delay circuit, and FIG. 7 shows a mount (layout) structure of the same circuit.
In contrast to the structure shown in FIG. 5, the layout structure shown in FIG. 7 is arranged such that a gate 7A bridging two diffusion layers 3 and 4 has two linear portions 7a and 7b. Conduction channels formed from electrodes Vdd and Vss to an output terminal 14 are formed in the direction of the widthwise distance between two gates arranged in parallel to each other in one diffusion layer (3 or 4), so that the conduction channel length is long. According to this structure where attention is focused on each of the transistors forming the complementary transistor structure, the ON-resistance of the gate is increased by connecting plural transistors in series from one power source terminal to the output terminal. The delay amount can thus be increased more than a normal gate circuit.
Patent Literature 1: Japanese Patent Laid-Open No. 4-94557 (page 2, FIGS. 2 and 5)
If a delay circuit is constructed with use of the gate circuit shown in FIG. 5 according to the prior art described above, it is necessary to use plural uniform gate circuits connected in series in order to ensure a delay amount. As a result, the circuit has a large size, so that the mount efficiency is lowered.
Alternatively, if a delay circuit is constructed with use of the gate circuit shown in FIG. 7, the delay amount of each gate circuit is greater than that in the circuit shown in FIG. 5. However, the delay circuits need a large size in the direction between the input and output. Further, if it is arranged within the distance width of the power source terminal (power source line), like the gate circuit shown in FIG. 5, the mount efficiency cannot be improved in the direction of the distance width. As a result, a great improvement in mount efficiency cannot be expected.
The present invention has been made to solve the above problems and has an object of providing a gate circuit capable of raising space efficiency by improving the mount density when a delay circuit is constructed with use of the gate circuit, and the delay circuit using the gate circuit.